1. Field of Invention
The present invention relates to a conductive line structure, a manufacturing method thereof and a manufacturing method of a thin film transistor (TFT) display array, and particularly to a multi-layered complementary conductive line structure capable of solving the line resistance problem, a manufacturing method thereof and a manufacturing method of a TFT display array having the conductive line structure.
2. Description of the Related Art
Along with an increasing display panel size, the total length of the metal conductive lines in a TFT display is accordingly increased, which makes the time delay phenomenon a remarkable problem for a good display quality. Since a LCD TV panel over 37 inch size today generally has a 16:9 panel aspect ratio of width over height, the RC (resistance-capacitance) delay time problem caused by scan lines are more significant than data lines. To solve the RC delay problem for a better display quality, most manufacturers take a bilateral driving mode. The scheme in bilateral driving mode needs more IC drivers, not to mention a higher packaging cost is necessary.
FIG. 1 is a diagram of a conventional TFT display array structure. Referring to FIG. 1, a TFT array 10 comprises a plurality of pixels 18 arranged in an array. Each pixel 18 includes a TFT 16, and a plurality of gate scan lines 14 in horizontal parallel arrangement and a plurality of data lines 12 in vertical parallel arrangement together partition every pixel. Each TFT 16 is connected to and driven by a pair of the gate scan line 14 and a data line 12.
FIG. 2 is a pixel structure diagram of a conventional TFT display. Referring to FIG. 2, each pixel 18 has a TFT 16, the gate scan line 14 connects the gate terminal 26 of the TFT 16 and the data line 12 connects the source terminal 20 of the TFT 16. The drain terminal 22 of the TFT 16 is connected to a pixel electrode 28 of the pixel 18. TFT 16 serves as a switch component for controlling switches through the gate scan line 14 and connecting the data line 12 to the pixel electrode 28 of the pixel 18.
FIG. 3 is a schematic 3-dimentional drawing showing a cross portion of a data line and a gate scan line. Referring to FIG. 3, a data line 12 and a gate scan line 14 belong to different metal layers, respectively and are isolated from each other by an isolating layer 30, and the two lines are not connected to each other. As described above, along with an increasing display panel size, the total length of the metal connection lines in a TFT display and the corresponded resistance of the data lines and the gate scan lines are noticeably increased, which makes the time delay phenomenon a remarkable problem for a good display quality.